A dynamic random access memory (DRAM) is a semiconductor device for storing digital information. Data, as digital information, can be written to and read from a DRAM. DRAMS are fabricated using integrated circuit technology and are powered by a supply voltage called Vcc.
FIG. 1 is a schematic of a DRAM memory cell 100. A DRAM has many memory cells. Typically, each memory cell comprises a combination of a cell access transistor 101 and a capacitor C 103. The cell access transistor 101 is generally an n-channel transistor having a slightly higher threshold voltage than a regular n-channel transistor. In the memory cell, digital information is represented by a charge stored in the capacitor C 103. However, the capacitor C 103 will lose its charge unless it is regularly recharged or refreshed. When a memory cell stores a "one" value, the capacitor is charged, and when the memory cell stores a "zero" value, the capacitor is discharged. In addition, reading the information stored in the memory cell 100 destroys the contents of the memory cell. After reading the memory cell 100, the memory cell contents need to be restored. Each memory cell 100 connects to a word-line (WL) 105 and a bit-line 107. To fully restore a "one" level to the memory cell capacitor C 103, the word line driver typically outputs a voltage on the word line 105 that exceeds the voltage applied to the bit-line 107, the supply voltage Vcc, by at least the amount of the threshold voltage Vth of cell access transistor 101 so that the capacitor C 103 can be charged up to the same voltage level as the bit-line. Therefore, DRAMs need an internal high voltage generator, commonly called Vpp generator, to generate or "pump" up the supply voltage Vcc to a required voltage level called Vpp.
FIG. 2 is a general block diagram of a Vpp generator 200 to supply a pumped-up Vpp voltage. The Vpp generator 200 has a pump circuit 210 and a Vpp regulator 220 which are connected in series. The pump circuit 210 comprises an oscillator 230 and a pump driver 240. The pump circuit 210 outputs a pumped-up voltage called Vpp, and Vpp is fed back to the Vpp regulator 220. The Vpp regulator 220 outputs an enable signal to the oscillator 230. If Vpp is below a required voltage level, the enable signal output by the Vpp regulator 220 is "on." When the enable signal is "on," the oscillator 230 continues to run and the pump driver 240 increases the voltage Vpp. When Vpp reaches the required voltage level, the Vpp regulator 220 turns the enable signal to "off." When the enable signal is off, the oscillator 230 stops running and the pump driver 240 no longer increases the voltage Vpp.
FIG. 3 is a schematic diagram of the prior art Vpp regulator 220 of FIG. 2. The circuit comprises a memory cell access transistor M3, two n-channel transistors M4, M5, two p-channel transistors M1, M2, and an inverter 11. In this and the following schematics, the following conventions are used. The memory cell access transistor, e.g., M3, is drawn with a "c" between the source and the drain. A ".cndot." inside the transistor is placed closest to the transistor's source. A p-channel transistor has an ".smallcircle." on its gate, while an n-channel transistor has no ".smallcircle.." If a substrate wire is not shown, for an n-channel transistor the substrate connects to ground, and for a p-channel transistor, the substrate connects to Vcc. The numbers beneath the reference character near the transistor indicate the transistor's preferred width and length. For example, memory cell access transistor M3 has a width of 0.6 microns and a length of 0.35 microns.
To accurately regulate the pumped-up voltage Vpp, this individual memory cell access transistor M3 has characteristics which match the memory cell access transistors in the whole memory array. The threshold voltage of transistor M3 matches the threshold voltage of the memory cell access transistors, Vth (cell).
Referring also to FIG. 4a, a graph shows the result of a simulation of the prior art Vpp regulator circuit of FIG. 3 when Vcc equal to 3.3 volts. When Vpp&lt;Vcc+Vth(cell), memory cell access transistor M3 is turned off. Since M3 is turned off, the voltage at node N1 follows Vpp and increases. The source to gate voltage of M2 is less than the threshold voltage of p-channel transistor M2. Therefore, M2 is off. Since the voltage at the gate of n-channel transistor M4 is Vcc, M4 is turned on. Therefore, node N2 is at ground, a low state, and the inverter I1 outputs an enable signal at Vcc, a high state, to turn on the oscillator.
As voltage Vpp approaches Vcc+Vth(cell), memory cell access transistor M3 begins to turn on. The voltage at node N1 stops increasing. As Vpp further increases, the source to gate voltage of M1 and M2 eventually exceeds the threshold voltage of the p-channel transistors M1 and M2. M1 and M2 turn on. The voltage at node N2 begins to increase. When node N2 reaches the voltage level that the inverter I1 recognizes as "high," the enable signal output by inverter I1 becomes "low" and turns off the oscillator. Therefore, in the prior art, Vpp is always regulated at to a voltage approximately equal to Vcc+Vth(cell).
In summary, the enable signal shuts off the pump circuit (not shown) when the exact voltage required to fully turn on the memory cell access device is attained. In other words, when Vpp rises sufficiently to turn on n-channel transistor M3 to allow current to flow, the enable signal becomes `LOW` to shut off the pump circuit (not shown).
FIG. 4b is a graph of the result of a simulation of the prior art Vpp regulator circuit of FIG. 3 for various supply voltages. The x-axis is Vpp and the y-axis is the enable signal voltage. The enable signal voltage is shown for five different supply voltages Vcc's: 2.3 V, 2.8 V, 3.3 V, 3.8 V and 4.3 V. Typically, the supply voltage is about 3.3 volts for normal operation. For each level of Vcc shown, the pumped-up voltage Vpp exceeds the supply voltage Vcc by approximately 2 V. Therefore, in the prior art, the Vpp regulator sets the Vpp level at about the supply voltage plus the threshold voltage of the memory access transistor, approximately Vcc+Vth(cell).
The prior art Vpp regulator sets Vpp to approximately Vcc+Vth(cell). This level becomes very high when the supply voltage Vcc is high. It may stress the devices severely and cause reliability problems. For example, at supply voltages Vcc of 3.8 V and 4.3 V, Vpp becomes 6 V and 6.6 V, respectively, which may cause the overstress and shorten the lifetime of the DRAM. Therefore, there is a need for a method and apparatus to clamp the pumped-up voltage Vpp to a safe operating level for a range of high supply voltages Vcc to prevent overstress of DRAMs.